1. Field of the Invention
The invention pertains generally to computers. In particular, it pertains to computer memory bus operations.
2. Description of the Related Art
Many conventional computer systems support various types of transfers over a bus, including a burst read mode. In the burst read mode, which is typically a synchronous clocked operation, a multi-transaction transfer is set up by specifying the starting memory address to begin the transfer from, and the amount of data to be transferred. After the transfer is initiated, it runs to completion, using as many bus transactions as necessary to transfer the specified amount of data. Since the parameters of a burst transfer must be set up, it creates an initial overhead penalty in the form of extra instructions that must be executed by the processor before the transfer can begin. However, once the transfer has begun, it can continue without any involvement by the processor, thus freeing up the processor to perform other tasks while the transfer is taking place. A burst transfer therefore incurs a greater overhead load at the beginning, but is much more efficient once the actual data transactions have begun.
A disadvantage of the burst transfer is that, if it involves transferring a large amount of data, the transfer will occupy the bus for a long time period, and may make the bus unavailable for other higher-priority transfers that request the bus during the burst transfer. Some time-critical transfers may not be able to wait, and must be able to interrupt the burst transfer to take control of the bus. This is accomplished by stopping the burst transfer that is in progress, turning over the bus to the requesting device, and resuming the interrupted transfer when the bus becomes available again. Unfortunately, some of the initial overhead functions must again be incurred to resume the transfer, causing this interruption to be inefficient.
In addition to this overhead burden, a memory latency period is also incurred at the beginning of a transfer, but not in subsequent transactions within that transfer. Typically, multiple words are sensed in parallel from the memory""s storage circuits and placed in an output buffer. These words are then output to the bus one at a time. The first read transaction will take longer than one clock cycle, since the address lines must be read first to determine what address to read the initial data from. After applying the address to the memory""s selection circuits, a further delay is encountered while waiting for the sense operation to complete. But after the first sense operation, delays are negligible. A current address can be maintained with an incrementing address counter in the memory interface and the address does not have to be placed on the bus again. Also, a background read can sense the next set of data while the previous set is being output onto the bus. By the time the words have been output from the output buffer to the bus, the sense operation has completed and the next set of words is placed in the output buffer. Thus, after the first sense operation, any subsequent sense delays generally do not cause additional delays for the bus because they each take place during the transfer of the previous set of words.
However, if the burst transfer is interrupted and later resumed, the address in a conventional address counter is lost and must be placed on the bus again when the transfer resumes. The memory device must then access the selected address, so all of the initial bus latencies are experienced again. These latency delays are repeated as many times as the burst transfer is interrupted.
FIG. 1 shows a timing diagram of the bus signals for a conventional system. A xe2x80x9c#xe2x80x9d symbol at the end of a signal name indicates the signal is asserted when it is low, and deasserted when it is high. To begin a burst read operation, a particular memory device is selected by asserting Chip Enable (CE#) to that device. This activates the selected memory device, bringing it out of low-power standby mode. In bus clock (BUS CLK) cycle 2, the initial address is placed on the address lines ADDR, and the Address Valid signal ADV# is asserted to cause the selected memory device to place the address in its address counter. Write Enable (WE#) remains deasserted to indicate this is a read operation. On a subsequent cycle, Output Enable (OE#) is asserted to enable the data line drivers of the memory device, which then places data on data lines DQ(15:0) at cycle 6. MEM CLK is the memory device""s internal clock, and CDMSEL is a multiplexer output that selects which of the words in the output buffer is to be placed on the bus next. WAIT is asserted by the memory device whenever it needs to indicate it cannot respond in the current bus clock cycle.
To interrupt the burst, CE# is deasserted as shown at clock cycle 7. When the burst is resumed by reasserting CE# (shown at clock cycle 8, although multiple cycles will typically occur between deasserting and reasserting CE#), ADV# must be asserted again to load the current address from address lines ADDR before data can again be transferred. Additional latency is incurred waiting for the sense operation to complete before that data will be available for placing on the bus. Thus each interruption in a burst transfer results in latencies due to both specifying the address on the bus and performing the initial sense operation within the memory circuits.